SystemVerilog parameter placeholder shows wrong value

If there are two modules in the same file and the same parameter name is used in both modules, the placeholder of second parameter (i.e. when mouse is on the parameter name) shows the first match value.

module a ();

  parameter a = 5;

  int x = a; // if mouse is on "a", it will show "parameter a = 5"

endmodule

module b ();

  parameter a = 7;

  int x = a; // here, the placeholder of a will show "parameter a = 5" which is wrong in the scope of "b" module.

endmodule